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| MC14106B Hex Schmitt Trigger The MC14106B hex Schmitt Trigger is constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. These devices find primary use where low power dissipation and/or high noise immunity is desired. The MC14106B may be used in place of the MC14069UB hex inverter for enhanced noise immunity or to "square up" slowly changing waveforms. http://onsemi.com MARKING DIAGRAMS 14 PDIP-14 P SUFFIX CASE 646 1 14 SOIC-14 D SUFFIX CASE 751A Unit V V mA mW C C C TSSOP-14 DT SUFFIX CASE 948G 1 A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week 1 14 14 106B ALYW 14106B AWLYWW MC14106BCP AWLYYWW * Increased Hysteresis Voltage Over the MC14584B * Supply Voltage Range = 3.0 Vdc to 18 Vdc * Capable of Driving Two Low-power TTL Loads or One Low-power * * Schottky TTL Load Over the Rated Temperature Range Pin-for-Pin Replacement for CD40106B and MM74C14 Can Be Used to Replace the MC14584B or MC14069UB MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.) Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 2.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Value - 0.5 to +18.0 - 0.5 to VDD + 0.5 10 500 - 55 to +125 - 65 to +150 260 ORDERING INFORMATION Device MC14106BCP MC14106BD MC14106BDR2 MC14106BDT MC14106BDTR2 Package PDIP-14 SOIC-14 SOIC-14 TSSOP-14 Shipping 2000/Box 55/Rail 2500/Tape & Reel 96/Rail 1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. v v TSSOP-14 2500/Tape & Reel (c) Semiconductor Components Industries, LLC, 2000 1 March, 2000 - Rev. 3 Publication Order Number: MC14106B/D MC14106B LOGIC DIAGRAM 1 3 5 9 11 13 VDD = PIN 14 VSS = PIN 7 2 4 6 8 10 12 EQUIVALENT CIRCUIT SCHEMATIC (1/6 OF CIRCUIT SHOWN) http://onsemi.com 2 III I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I III II IIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I II II IIII I I II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I III I I I I I I I I I III II IIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIII I I II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I III II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIII I I III I I I I I I I I I III II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I III II IIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIII I I II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III III I I I I I I I I I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIIIII I II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII 3. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 4. The formulas given are for the typical characteristics only at 25_C. 5. To calculate total supply current at loads other than 50 pF: where IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.001. 6. VH = VT+ - VT- (But maximum variation of VH is specified as less that VT+ max - VT- min). ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Total Supply Current (4.) (5.) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) Quiescent Current (Per Package) Input Capacitance (Vin = 0) Input Current Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) Threshold Voltage Positive-Going Hysteresis Voltage Output Voltage Vin = VDD (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Vin = 0 Negative-Going Characteristic IT(CL) = IT(50 pF) + (CL - 50) Vfk "1" Level "0" Level Source Sink Symbol VH (6.) VOH VOL VT+ VT- IOH IDD Cin IOL Iin IT VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 15 -- http://onsemi.com - 3.0 - 0.64 - 1.6 - 4.2 4.95 9.95 14.95 0.64 1.6 4.2 MinIII Max 0.9 2.5 4.0 2.2 4.6 6.8 0.3 1.2 1.6 MC14106B -- -- -- -- -- -- -- -- - 55_C 3 0.1 3.6 7.1 10.8 0.25 0.5 1.0 0.05 0.05 0.05 2.8 5.2 7.4 2.0 3.4 5.0 -- -- -- -- -- -- -- -- -- -- -- - 2.4 - 0.51 - 1.3 - 3.4 4.95 9.95 14.95 0.51 1.3 3.4 Min 0.9 2.5 4.0 2.2 4.6 6.8 0.3 1.2 1.6 -- -- -- -- -- -- -- -- IT = (1.8 A/kHz) f + IDD IT = (3.6 A/kHz) f + IDD IT = (5.4 A/kHz) f + IDD 0.00001 Typ (3.) 0.0005 0.0010 0.0015 - 4.2 - 0.88 - 2.25 - 8.8 25_C 0.88 2.25 8.8 5.0 1.9 3.9 5.8 2.9 5.9 8.8 1.1 1.7 2.1 5.0 10 15 0 0 0 0.1 3.6 7.1 10.8 0.25 0.5 1.0 0.05 0.05 0.05 Max 7.5 2.8 5.2 7.4 2.0 3.4 5.0 -- -- -- -- -- -- -- -- -- -- - 1.7 - 0.36 - 0.9 - 2.4 4.95 9.95 14.95 0.36 0.9 2.4 Min 0.9 2.5 4.0 2.2 4.6 6.8 0.3 1.2 1.6 -- -- -- -- -- -- -- -- 125_C 1.0 3.6 7.1 10.8 0.05 0.05 0.05 Max 7.5 15 30 2.8 5.2 7.4 2.0 3.4 5.0 -- -- -- -- -- -- -- -- -- -- -- mAdc mAdc Adc Adc Adc Unit Vdc Vdc Vdc Vdc Vdc pF MC14106B Vout , OUTPUT VOLTAGE (Vdc) III I I I I I IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I IIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C) Characteristic Symbol tTLH VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 Min -- -- -- -- -- -- -- -- -- Typ (7.) 100 50 40 100 50 40 125 50 40 Max 200 100 80 200 100 80 250 100 80 Unit ns Output Rise Time Output Fall Time tTHL ns Propagation Delay Time tPLH, tPHL ns 7. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. PULSE GENERATOR VDD 14 OUTPUT INPUT 7 VSS CL tPHL OUTPUT tf 90% 50% 10% tr 20 ns INPUT 90% 50% 10% tPLH 20 ns VDD VSS VOH VOL Figure 1. Switching Time Test Circuit and Waveforms VDD 0 0 VT- VH Vin, INPUT VOLTAGE (Vdc) VT+ VDD Figure 2. Typical Transfer Characteristics http://onsemi.com 4 MC14106B APPLICATIONS Vin VH VDD VH Vout VDD Vin VSS VDD Vin VSS VDD Vout VSS Vout VSS (a) Schmitt Triggers will square up inputs with slow rise and fall times. Figure 3. VDD (b) A Schmitt trigger offers maximum noise immunity in gate applications. VDD R tw Rs Vout C R tw = RC IN Rs Vout VDD VT+ C tw Useful as Pushbutton/Keyboard Debounce Circuit. Figure 4. Monostable Multivibrator http://onsemi.com 5 MC14106B 1 f R t2 t1 Vin R A C VDD Vin VT+ VSS VDD VT+ VSS Vout C * t1 [ RC ln VTT) V - * t2 1 f T DD [ RC ln VVDD - VT) -V - A [ RC ln VDD - VT - VDD - VT) VT) VT- *t1 + t2 & tPHL + tPLH VDD Vout VT+ VSS Useful in discriminating against short pulse durations. Figure 5. Astable Multivibrator Figure 6. Integrator C Vin R Vin + EDGE - EDGE - EDGE + EDGE VDD tw VDD tw = RC ln VT+ Useful as an edge detector circuit. Vin C C C R R R Figure 7. Differentiator Figure 8. Positive Edge Time Delay Circuit http://onsemi.com 6 MC14106B PACKAGE DIMENSIONS P SUFFIX PLASTIC DIP PACKAGE CASE 646-06 ISSUE M 14 8 B 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --- 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --- 10_ 0.38 1.01 A F N -T- SEATING PLANE L C K H G D 14 PL 0.13 (0.005) M J M DIM A B C D F G H J K L M N D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F -A- 14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. -B- 1 7 P 7 PL 0.25 (0.010) M B M G C R X 45 _ F -T- SEATING PLANE D 14 PL 0.25 (0.010) M K TB S M A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 http://onsemi.com 7 MC14106B PACKAGE DIMENSIONS DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948G-01 ISSUE O 14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C --- 1.20 --- 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0_ 8_ 0_ 8_ 0.10 (0.004) 0.15 (0.006) T U S M TU S V S N 2X L/2 14 8 0.25 (0.010) M L PIN 1 IDENT. 1 7 B -U- N F DETAIL E K K1 J J1 0.15 (0.006) T U S A -V- C 0.10 (0.004) -T- SEATING PLANE D G H DETAIL E ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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